1. Field of the Invention
The present invention relates to a method of controlling film thinning of a semiconductor wafer for a solid-state image sensing device. More specifically, the present invention relates to a method of controlling film thinning of a semiconductor wafer for a solid-state image sensing device in a back-illuminated type solid-state image pick-up apparatus in which a solid-state image sensing device is formed on a surface layer of a semiconductor wafer and light is made incident from a rear surface side that is opposite to the side where the solid-state image sensing device is formed.
2. Description of the Related Art
In a front-illuminated type CMOS solid-state image pick-up apparatus, there is multi-layer wiring in a light path of an incident light, especially in a light path of a gradient light in a periphery portion of an effective pixel area. Therefore, it is known that since the multi-layer wiring blocks light penetration, efficiency of light utilization is undermined and sensitivity also decreases. As a conventional technology directed to resolving this problem, a back-illuminated type CMOS solid-state image pick-up apparatus has been developed in which multi-layer wiring is formed on a front surface side of a silicon wafer and light is made incident from a rear surface side of the silicon wafer (for examples, Related Arts 1-3).
In the following, with reference to a flow sheet of FIG. 4, a manufacturing method of a conventional back-illuminated type solid-state image pick-up apparatus disclosed in FIGS. 6-8 of Related Art 2 is explained.
First, an epitaxial SOI wafer 102 is prepared in which an epitaxial film 101 is formed on a surface of an SOI wafer 100 (FIG. 4a). In the SOI wafer 100, an active layer 105 is formed on a surface of a silicon wafer 103 via an embedded silicon oxide film (SiO2 film) 104, the active layer 105 being a thin film and the silicon wafer 103 being made of a silicon single crystal. The epitaxial film 101 is epitaxially grown on a surface of the active layer 105.
Next, a pixel separation area portion of an image pick-up area, a semiconductor well area portion, and a photo diode 106 as a photo sensor, are formed in the epitaxial film 101 from a front surface side thereof (FIG. 4b).
After that, a source-drain area that constitutes a plurality of MOS transistors for reading out a signal charge is formed on each unit pixel cell of the epitaxial film 101, and a gate electrode is formed via a gate insulator film. Next, a source-drain area that constitutes another CMOS transistor is formed on a peripheral circuit portion, and a gate electrode is formed via a gate insulator film. Further, on the surface of the epitaxial film 101, a multi-layer wiring layer 109 is formed in which a multi-layer wiring 108 is formed in an interlayer insulator film 107.
Next, on the surface of the multi-layer wiring layer 109, an adhesive layer 110, which is made of a silicon oxide film, is formed. A Chemical Mechanical Polishing is applied to the surface of the adhesive layer 110 to planarize the surface of the adhesive layer 110 (FIG. 4c). The epitaxial film 101, which has the photo diode 106 and the like formed therein, and the multi-layer wiring layer 109 constitute a solid-state image sensing device 117 of a CMOS type.
After that, a support substrate 112, which is made of single crystal silicon and has another adhesive layer 111 (which is made of silicon oxide film) formed on a bonding interface side, is bonded to the surface of the multi-layer wiring layer 109 to form a bonded wafer 113 (FIG. 4d).
After that, the bonded wafer 113 is flipped over, and the silicon wafer 103 is ground by using a grinding wheel until a residual thickness of 10-30 μm is reached (FIG. 4e).
After that, by using the embedded silicon oxide film 104 as an etching stop layer, the residual portion of the silicon wafer 103 is removed by etching with a KOH solution (FIG. 4f). Using a KOH solution as an etching solution allows a selectivity between the silicon wafer 103 and the embedded silicon oxide film 104 to increase to Si:SiO2=100:1 or above. As a result, it is possible to etch the silicon wafer 103 at a rate of 0.2-10 μm/min, and use the embedded silicon oxide film 104 as an etching stop layer.
After that, film thinning is performed by removing the embedded silicon oxide film 104 with a hydrofluoric acid so as to expose the rear surface of the active layer 105 (FIG. 4g).
Next, a pad aperture is formed at a required location of the active layer 105, and a terminal area is formed which includes interior portion of the aperture and connects to wiring. After that, a color filter 114 and a micro lens 115 are sequentially formed at a location corresponding to the photo diode 106 of each pixel (FIG. 4h). By doing this, a CMOS solid-state image pick-up apparatus 116 of a back-illuminated type is manufactured.    [Related Art 1] Japanese Patent Laid-Open Publication No. 2008-258201    [Related Art 2] Japanese Patent No. 4046067    [Related Art 3] Japanese Patent Laid-Open Publication No. 2005-353996
In this way, according to the method of Related Art 2, first, in the SOI wafer 100, the CMOS solid-state image sensing device 117 is fabricated from the interior of the epitaxial film 101 across the surface thereof. After that, the support substrate 112 is bonded to the rear surface side of the silicon wafer 103. Next, by using an etching stop method, the silicon wafer 103 is thinned until a necessary thickness is reached, and the CMOS solid-state image sensing device 117 is repositioned on the support substrate 112.
According to this method, it is possible to accommodate a request from the device manufacturing sector in recent years regarding reduction in thickness variation of the CMOS solid-state image sensing device 117. When thickness variation occurs, variation in incident intensity of light incident to the CMOS solid-state image sensing device 117 occurs, and it is possible for color unevenness to occur. However, the conventionally used epitaxial SOI wafer 102, in which the epitaxial film 101 is formed on the thin film active layer 105, was expensive. Furthermore, since the epitaxial film 101 is formed on the thin film active layer 105, defects such as slips and the like occur frequently, as compared to the case in which an epitaxial film is formed on a single layer silicon wafer.
In order to solve this problem, a method is developed in which, in place of an SOI wafer, an epitaxial silicon wafer, in which two layers of epitaxial films are formed on the surface of a silicon wafer, is used, and film thinning of the silicon wafer is performed by using etching stop. However, according to this method, although an ideal dopant concentration ratio can be maintained at an early stage of the use of the CMOS solid-state image pick-up apparatus 116, impurity diffusion occurs when a device heat treatment or the like is applied. Therefore, the dopant concentration ratio is no longer suitable for etching stop, and a gradual concentration gradient is generated, and thus, a nonuniform etching is being carried out, which resulted in the above described thickness variation problem of the CMOS solid-state image sensing device 117.
Further, as another conventional technology directed to reduction in thickness variation of a CMOS image sensing device, as disclosed in Related Art 3, a method has been developed in which an end-point detector (polishing stop layer) is formed on the surface of the semiconductor substrate as an embedded layer of a material that is different from the semiconductor substrate. The semiconductor substrate is subjected to film thinning by polishing the semiconductor substrate from the rear surface thereof until a position facing the end-point detector is reached. After that, a solid-state image sensing device is formed on the front surface side of the semiconductor substrate, and a support substrate is bonded to the front surface side of the semiconductor substrate. By doing this, a semiconductor apparatus including a back-illuminated type solid-state image sensing device is manufactured. However, in this method, an end-point detector, which is a polishing stop layer, has to be made, which increases the number of processes and results in high cost.